Saion K. Roy recently graduated with a Ph.D. from University of Illinois Urbana-Champaign and joined Northeastern University as a post-doctoral fellow to explore security issues in computing. As part of his COCOSYS research, Saion became the first to discover security vulnerabilities of eNVM-based in-memory computing (IMC) architectures and experimentally validate his ideas on a real-life 22nm MRAM-based IMC chip prototype. In this process, he brought security alongside energy efficiency, accuracy, and robustness as an important metric to optimize for. Prof. Shanbhag praised Saion’s achievements, saying, “Congratulations to Saion for his outstanding doctoral research encompassing modeling, analysis, design, and benchmarking of in-memory computing (IMC) architectures, and on being the first to experimentally identify security vulnerabilities of resistive IMCs. His work would not be possible without strong support from the COCOSYS community. We can all be proud of Saion and his accomplishments.” Saion’s impactful work, which bridges algorithm-hardware co-design and system security, continues to influence the IMC research community as he now focuses on machine learning accelerator security at NEU.
1. Tell us about your experience as a CoCoSys research scholar advised by theme 1 leader Naresh Shanbhag. What did you learn?
Working as Prof. Shanbhag’s Ph.D. student was an extraordinary learning experience. Prof. Shanbhag has a remarkable ability to foresee the long-term impact of research problem statements, significantly shaping my research approach. This perspective allowed me to see how my research fits into the broader landscape, enabling me to formulate well-defined, impactful research problems in my resistive IMC research [ESSCIRC’23, JSSC’24, JxCDC’24, ICCAD’24, IEDM’24]. I also contributed to the in-memory computing (IMC) benchmarking project [CICC’22, OJ-SSCS’22], which has now become an important resource for IMC researchers to evaluate and compare their designs with state-of-the-art works. Seeing the effort we invested in creating the repository (https://github.com/UIUC-IMC/UIUC-IMC-Benchmarking) now benefiting the wider community is deeply fulfilling—another testament to Prof. Shanbhag’s visionary leadership.
2. How did your research support the goals of CoCoSys?
My Ph.D. research focused on resistive in-memory computing (IMC) architectures, contributing to Theme 2 on algorithm-hardware co-design. In the SNDR-boosted MRAM-based IMC work [ESSCIRC’23, JSSC’24], we proposed an algorithmic- and circuit-level accuracy boosting technique, which was validated with a 22nm FDX (GlobalFoundries) IC prototype. Additionally, our comprehensive analysis of energy-accuracy trade-offs in resistive IMCs using a chip-validated behavioral model [JxCDC’24] pointed out the fundamental accuracy limitations of resistive IMCs. Most recently, we looked into the security vulnerabilities of resistive IMCs employing algorithms that leverage the information on the non-idealities of resistive IMCs – revealing that they are vulnerable to model extraction attacks [ICCAD’24, IEDM’24]. The concepts used here were a link between the objectives of Theme 1 and Theme 2, fostering cross-stack research.
3. What were the key findings or contributions of your research?
As the research focusing on non-volatile memories for enabling in-memory computing (IMC) continues to grow, my work provides a critical insight: the maximum achievable accuracy for resistive IMCs is fundamentally limited by analog non-idealities at the device and circuit levels [ESSCIRC’23, JSSC’24, JxCDC’24]. To address these challenges, I explored algorithmic and circuit-level techniques to enhance accuracy—moving beyond the commonly employed noise-aware training methods tailored to specific DNN architectures. Furthermore, our findings revealed even when the inherent non-idealities in resistive IMCs may create the illusion of security, they are, in fact, susceptible to model-extraction attacks, enabling adversaries to retrieve weights stored in memory with high accuracy [ICCAD’24, IEDM’24].
4. What challenges did you face, and how did you overcome them?
One of the most valuable lessons I learned during my Ph.D. was the importance of patience, especially when the solution to a problem feels out of reach. Research often demands a significant investment of time and effort to understand and resolve complex issues truly. A Ph.D. requires both depth and breadth, and managing these effectively can make a big difference. I found it helpful to interleave my efforts across multiple projects, balancing my time based on the anticipated progress of each. In my case, the MRAM IMC chip design work and the resistive IMC analysis complemented each other seamlessly—insights from one informed the other, leading to strong results in both areas.
5. What are your short-term and long-term career goals?
I am currently a postdoctoral researcher at Northeastern University, focusing on the security of machine learning accelerators. My long-term goal is to secure a tenure-track faculty position.
6. What advice would you give to new CoCoSys research scholars?
CoCoSys is a highly interdisciplinary center that brings together professors, industry liaisons, and research scholars. The annual review meetings provide an excellent platform to receive constructive feedback on ongoing work and engage in conversations with experts from diverse domains, sparking new ideas and perspectives for research. Additionally, the weekly talks offer a valuable opportunity to showcase your work and connect with the broader research community.
References
[ESSCIRC’23] Roy, Saion K., et al., “Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation,” IEEE European Solid-State Circuits Conference (ESSCIRC), 2023.
[JSSC’24] Roy, Saion K., et al. “Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation.” IEEE Journal of Solid-State Circuits (JSSC), 2024.
[JxCDC’24] Roy, Saion K., and Naresh R. Shanbhag. “Energy-Accuracy Trade-offs for Resistive In-Memory Computing Architectures.” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2024.
[ICCAD’24] Roy, Saion K., and Naresh R. Shanbhag. “Energy-Accuracy Trade-offs for Resistive In-Memory Computing Architectures.” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2024 (to appear).
[IEDM’24] Roy, Saion K., and Naresh R. Shanbhag. “Energy-Accuracy Trade-offs for Resistive In-Memory Computing Architectures.” IEEE International Electron Devices Meeting (IEDM), 2024 (to appear).
[CICC’22] Shanbhag, Naresh R., and Saion K. Roy. “Comprehending in-memory computing trends via proper benchmarking.” IEEE Custom Integrated Circuits Conference (CICC), 2022.
[OJ-SSCS’22] Shanbhag, Naresh R., and Saion K. Roy. “Benchmarking in-memory computing architectures.” IEEE Open Journal of the Solid-State Circuits Society (OJ-SCCS), 2022.